1. Technical Field
This invention relates to electroplating and, in particular, to electrochemical deposition of metals, most particularly to the electrochemical deposition of copper into microscopic recessed features such as high aspect ratio trenches and vias as may occur in the fabrication and packaging of integrated circuits.
2. Description of Related Art
The art of integrated circuits is moving irresistibly towards increased density of components and faster operating speeds. One problem encountered in decreasing the size of components fabricated on an integrated circuit relates to the conductivity of metallic interconnections. Conventional integrated circuits use aluminum as a conductor but for future generations of submicron components, the conductivity of aluminum is not sufficiently high to give desired performance. Smaller dimensions for conductive interconnections lead to higher resistance and degraded circuit performance. The trend in modern integrated circuit design is to substitute higher conductivity copper for aluminum conductors.
While copper apparently has sufficiently high conductivity to handle the foreseen submicron electronic components, its use brings challenges as well. For example, copper (Cu) tends to diffuse readily into the insulator and other layers making up the integrated circuit, necessitating the interposition of special barrier layers to prevent Cu diffusion. Tantalum (Ta) and/or tantalum nitride (TaN) are common copper barrier layers. Such barrier layers may play dual roles; preventing unwanted diffusion of Cu and providing improved adhesion between the Cu metal and the underlying layer.
Conductive interconnections on integrated circuits typically take the form of trenches and vias. In modern submicron integrated circuits, trenches and vias are typically formed by a “damascene” or “dual damascene” process as described, for example, in the reference ULSI Technology, Eds. C. Y. Chang and S. M. Sze (McGraw-Hill, 1996, pp. 444-445.) In damascene processing, an interlayer dielectric (typically SiO2) is deposited atop a planarized layer containing, for example, a metal via. The top dielectric layer is patterned and etched, typically using conventional photolithographic procedures. Metal is then deposited into features and on the flat field region atop the features, typically first by CVD, PVD and then by electrodeposition. The metal layer is typically planarized resulting in the desired metallic pattern. Dual damascene processing is similar but makes use of two patterning and etching steps and typically fills features with metal spanning more than one layer in a single metallization step. A more complete description of damascene and dual damascene processing is found in the cited reference.
Thus, as the art moves towards integrated circuits having reduced feature sizes, it becomes increasingly difficult to form electrically conductive metallizations such as vias, contacts and conductors. Techniques for forming such metallizations include physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) and electrochemical deposition (also referred to as electroplating or electrodeposition) of metals such as copper. Electroplating is particularly well suited for the formation of small embedded damascene feature metallization due to the ability to readily control the growth of the electroplated film for bottom-up filling without voids, and due to the superior electrical conductivity characteristics of the electroplated film. However, there are also several obstacles which need to be overcome to fully realize these advantages.
One challenge facing dual damascene processing techniques noted above is the difficulty of initiating the growth of the metal film within recessed features without forming voids or seams. In typical PVD and some CVD processes, metal may preferentially deposit near the top of recessed features leading to a “bottleneck” shape. Further plating of metal onto the bottleneck may result in sealing the top of the feature before completely filling the feature with metal, creating thereby a void. Voids increase the resistance of the conductor over its designed value absence of planned-for conductor. Also, trapped electrolyte sealed in voids may corrode the copper. This may lead to degraded device performance or device failure in extreme cases. It would be desirable to provide electroplating processes that reduce or avoid such problems.
Another factor in metallization that needs to be considered is the time the metallization process takes to complete. As integrated circuits increase in complexity, the number of processing steps typically also increases. It is important in process economics (that is, keeping the cost per unit low) that such processes are reasonably rapid. Slow processes are disadvantageous in that increasing the work-in-progress increases the capital needs of the production process. A related consideration is the cost of the equipment needed to perform the required plating process. Thus, achieving reasonably high processing speeds and the ability to use less costly equipment are among the goals to be sought in an electroplating process.
A field layer of copper typically has a thickness from approximately 1000 Å to approximately 3000 Å lying atop a barrier layer of typically tungsten (W) Ta, TaN among other choices. Ta/TaN are the typically preferred materials for the barrier layer due to their relatively superior ability to mitigate the diffusion of Cu. Diffusion of Cu into the dielectric layer may ruin the circuit. An additional function of the barrier layer is to provide improved adhesion between the Cu field layer and the underlying dielectric layer. These barrier layers typically have thicknesses from approximately 100 Å to approximately 400 Å.
FIG. 1 is a top plan view of a typical section, 12, of a substrate, 10. Substrate 10 can be any article to be electroplated such as a semiconductor wafer upon which integrated circuits are fabricated. Formed in (or in a layer lying over) substrate 10 may be one or more trenches (a typical example is denoted by 14) and vias 16, 16a, 18. Although only a single trench 14, and three vias 16, 16a and 18, are illustrated for simplicity of discussion, it is understood that typically a large number of trenches and vias may be formed in substrate 10. It is common in a typical damascene or dual-damascene structure occurring in the fabrication of integrated circuits that vias occur in trenches to provide electrical contact between a conducting trench and a different level. This is depicted as 16a in FIG. 1. However, it is more convenient to describe trenches and vias in a non-overlapping configuration as depicted by 14, 16 and 18 for purposes of illustration, understanding thereby that vias occurring in trenches, 16a, are included.
Trench 14, vias 16, 16a and 18 are typically filled with an electrically conductive material such as a metal, e.g. copper, to form electrically conductive metallizations. For example, trench 14 may be filled to form a single layer conductor. As further examples, vias 16, 16a and 18 may be filled to form electrically conductive vias between interlevel conductors or to form contacts with semiconductor regions.
While a typical Cu seed layer onto which Cu is electroplated is 1000 Å to 3000 Å thick, the feature widths to be plated are commensurate in size. Present features are around 3000-4000 Å (0.3-0.4 micron, μm) and future features are expected to be in the range 1000-2000 Å. Thus, the number and size of the features can have a significant fractional effect on the projected surface area to be bottom-up fill electroplated and, therefore, on the current that must be delivered to effect electroplating in a reasonable time.
FIG. 13 depicts the effect of increasing the number of features on the current required to fill the trenches (for a fixed fill time). This means that the current required to fill features in a specified amount of time increases with the fraction of features on the surface. In addition to process economics, we demonstrate herein that the process of the present invention make use of the time for electrochemical reactions to occur on surfaces in effecting proper metal filling of features. Thus, the number of features on the surface to be coated (feature density) as well as the aspect ratio of the features determine the current needed to effect plating in a specified time.
FIG. 14 depicts the increase in surface area as an increasing fraction of the surface contains features, also illustrating the effect of increasing aspect ratio “AR,” for either trench or via. FIG. 14 presumes all trenches or all vias are the same size for purposes of illustration while practical integrated circuits will have both. This reinforces the conclusion of FIG. 13 that current may vary substantially from case to case (wafer type to wafer type) depending on the density and characteristics of the features.
FIG. 2 is a cross-sectional view of substrate 10 along the line II-II of FIG. 1. Referring to FIGS. 1 and 2, a seed layer 20 is typically formed over the entire substrate 10. Seed layer 20 is typically a conductive layer overlaying a barrier. The conductive layer is typically a sputtered (PVD) copper film although other conductors and other methods of deposition (such as CVD, PECVD, etc.) are not excluded. The barrier layers are typically Ta, TaN, Ti, TiN. The function of the seed layer is to allow electrical current to be distributed across substrate 10 thereby facilitating electroplating. Seed layer 20 typically covers the flat principal surface 22 of substrate 10 (hereinafter “field region 22”) and also lines the inside of trench, 14, and vias 16, 16a and 18.
In conventional electroplating, the thickness of seed layers 20 on sidewalls 14S, 16S, 18S of trench 14, vias 16, 18, respectively, is commonly significantly less than the thickness on field region 22. This can be understood by considering a simple geometric model wherein seed layers 20 are assumed to be deposited uniformly on field region 22 and the material which would have been deposited on field region 22 over trench 14, via 16 or 18 is evenly distributed within the respective trench or via. Thinning of the deposited layers in trenches and vias occurs according to this model due to the geometric fact that the trench or via presents more surface area to be coated by a given amount of coating material than would a substantially flat field region. It is useful to consider such layer thinning in terms of the aspect ratio (“AR”) of the feature. The AR of a trench or via is defined as the ratio of depth to width of the feature. Vias are depicted as square in FIG. 1 for convenience only. Vias can be square, circular or other cross section. The discussion of vias herein illustrated by reference to square vias is readily modified to apply to circular vias or to vias having other shapes as well. The AR is thus taken to be the ratio of the via's depth to a typical linear dimension in the plane of field region 22. A more precise definition of AR is not necessary for a description of the present invention.
Sidewall thinning according to this model is illustrated in FIG. 3. which depicts on the vertical axis the ratio of the feature sidewall thickness (trench or via) to the field region thickness of seed layer 20 depicted as a function of the AR of the feature. As shown in FIG. 3, as the AR becomes large, the thickness of seed layer 20 on sidewalls 14S, 16S, 18S can decline to less than 10% of the thickness of seed layer 20 on the field region 22.
In practice, the difficulty of depositing metal uniformly on the sides of trenches and vias to form a seed layer is further exacerbated by the following effects: 1) The generally directional nature of the PVD sputtering process, 2) greater deposition at the opening of the feature (“necking”) and 3) The relative inaccessibility of the feature to species transported by diffusion. Thus, in practice the portions of the sidewalls near the bottom of the feature tend to receive the thinnest seed layer.
Referring again to FIG. 2, the relative thinness of seed layer 20 on sidewalls 16S (for example) results in a relatively high electrical resistance R between field region 22 and the bottom 16B of via 16. This resistance R impedes electroplating current distribution to bottom 16B and consequently inhibits or prevents formation of an electroplated layer on bottom 16B. For similar reasons, increased resistance results between seed layer 20 and 14B, 18B, inhibiting or preventing formation of an electroplated layer on the bottom 14B of trench 14, and 18B of via 18, respectively. Similarly, increased resistance results between seed layer 20 and 14B, 18B.
FIG. 4 is a cross-sectional view of substrate 10 along the line II-II of FIG. 1 after electroplating in accordance with conventional electroplating methods. As shown in FIG. 4, an electroplated layer 24 has been electroplated on substrate 10 and in trench 14, vias 16, 18. Often due to the increased resistance encountered in delivering current to bottom 16B of via 16, a teardrop shaped void 26 can be formed in via 16 by such electroplating methods. The specific shape of the voids or seams formed in a feature generally depends on the AR of the feature, the electroplating conditions and other factors.
Since via 18 has a smaller AR than via 16 (in this illustration), seed layer 20 may have a thickness on sidewalls 18S sufficient to support an electroplating current to bottom 18B. Nevertheless, seams/voids may form, depicted as 28, if conditions for bottom-up filling (current, electrolyte, additive concentration, etc.) are not achieved
Voids and seams in electroplated features are undesirable for several reasons. Voids and seams disrupt the electrical continuity of the resulting metallization and hence unpredictably increase the electrical resistance. In extreme cases, voids and/or seams may result in an open circuit. Furthermore, the voids and seams can trap impurities, including the acid plating solution. Entrapped acid plating solution can corrode the circuit and add significant internal pressure as the circuit/chip heat during operation. Device failure may result.
Accordingly, the present invention relates to an improved method of reliably electroplating high AR features including methods of reducing or eliminating the formation of voids and seams in electroplated features.